Abstract
The design of ultra-low power (ULP) integrated circuits for Systems-On-Chip (SoCs) requires consideration of both flexibility and robustness during low-energy operation. Due to their quadratic relationship, the strongest design knob for reducing energy on-chip is the supply voltage. By operating digital circuits in the subthreshold region, using a supply voltage that falls below the threshold of the device, designers can minimize energy per operation at the cost of a performance penalty. However, there are many applications with low throughput requirements that can benefit from these energy savings. For example, systems that process biomedical data such as ECG, EEG, and EMG require sampling and processing rates on the order of kHz, making subthreshold operation feasible. The result of these substantial energy improvements is an emerging application space for these ULP SoCs in batteryless sensor nodes capable of running on energy harvested from the surrounding environment alone.
This work presents two versions of a highly integrated, flexible SoC platform targeted for Internet-of-Things (IoT) applications. These SoCs support multiple sensing modalities, extract information from data flexibly across applications, harvest and deliver power efficiently, and communicate wirelessly. The first version of the chip acquired ECG data, extracted the heart-rate, and transmitted the raw signal operating off of harvested energy while consuming 19μW. The first revision of the chip was tested end-to-end for motion capture with an ADXL362Z accelerometer (over SPI) while powered from indoor solar by an integrated power management unit. The chip consumed 6.45μW while streaming raw motion data wirelessly over the UWB radio.
To enable ULP operation, low power techniques need to be utilized across the hierarchy from the system-level down to the low-level circuit design. When focusing on digital design and processing, energy reductions can be achieved by modifying algorithm complexity, system or block-level architecture, and/or using leakage reduction techniques such as fine-grained clock and power gating. This dissertation introduces and explores these techniques for digital signal processing circuits and evaluates their system-level impacts. Multiple examples are discussed including: reducing memory overheads using approximate coefficients for an FIR filter, block-level error analysis of a logarithm unit and its impacts on system-level accuracy in voice activity detection, and the development of a ULP, scalable DSP fabric for flexible on-chip processing. The proposed methods evaluate the accuracy, area, power, and latency metrics for these block-level modifications and discuss the system-level consequences. The impact of these design decisions reduces overall power consumption without compromising system flexibility. The solutions presented in this work are by no means comprehensive; however, a general framework is built in this dissertation that can become a basis for further innovation and expansion.
