Circuit Design for FPGAs in Sub-Threshold Ultra-Low Power Systems

Field programmable gate arrays (FPGAs) are one of the most promising programmable devices in the era of ubiquitous computing. With low power systems limited by the design cost, energy consumption, portability requirement, and flexibility demands, FPGAs compensate the gap between Application Specific Integrated Circuits (ASICs) and General Purpose Processors (GPPs). Driven by the requirements of very small form-factor, long lifetime, and low energy consumption to support the vision of ubiquitous computing, the design of a sub-threshold FPGA will provide energy efficient digital circuits for a variety of ultra low power ubiquitous systems at low unit cost. However, studies show that 60% - 70% of power is dissipated in the FPGA interconnect fabrics, and also interconnect dominates delay and area in modern FPGAs. Motivated by the energy efficient design goal, this thesis proposes an optimization work in sub-threshold FPGA design which focuses on the FPGA interconnect. A voltage scaling technique based on a configurable header structure in the FPGA interconnect is proposed to show the potential of further reducing energy consumption in the FPGA interconnect. Finally, the thesis also presents a design work of a 145mV (from chip measurement) single ended level converter which can be used both in an FPGA circuit and a low voltage IC. This sub-threshold charge pump-based level converter can further extend the shifting ability, thus lowering the system threshold voltage. Two chips are fabricated for the proposed work in a 130nm CMOS technology, and simulation and measurement results are presented for both ICs.