Breaking the Power Delivery Walls using Digitally-Controlled Integrated Regulation

Integrated power regulation has become an essential tool in the arsenal of techniques that allow the semiconductor industry to continue Moore’s law of exponential integration in sub-20nm CMOS technology. While form factor constrains the quality of the integrated passives, switching losses and quiescent current consumption of the regulators limit their usage to coarse-grained power management. Another significant design trend in these nano-scale nodes is the increasing use of digitally-assisted analog solutions to leverage the superior switching characteristics of CMOS technology. The introduction of 3D stacked memory has renewed interest in vertical integration in the form of 3D-IC design. However, the predicted 3D-IC scaling, from dual-layer to many-layers, is stalled by the more fundamental “3D versus 2D” power mismatch in the power delivery network (PDN). While load current increases with additional vertical layers, the 2D surface area for delivering power and the power-bump numbers do not scale proportionally, creating a power delivery mismatch or “wall”.
This dissertation focuses on digitally-assisted circuit/architecture to improve integrated power regulation beyond state-of-the-art for system-on-chip design in nano-scale CMOS process nodes in both 2D and 3D-IC circuits. The primary contributions of this work are:
(1) Design and implementation of digitally-controlled low-dropout regulators with improved figure-of-merit (FOM), catering to a wide range of applications. The first “truly” hybrid IVR architecture is proposed, regulating a graphics core with 50% reduced voltage droop. Additionally, a digitally-adaptive LDO topology is proposed, using system power-modes information to regulate quiescent current loss in energy-harvesting architecture, achieving a FOM of 4.44ps.
(2) Cross-layer design explorations of multi-output switched-capacitor-assisted charge-recycled power regulation (also known as Voltage Stacking) to break the power delivery walls in 2D and 3D-IC. Voltage stacking (V-S), with its differential regulation, improves average power efficiency to more than 90% with superior power density. This claim has been validated with simulations using power-traces from architectural benchmarks (Parsec) and proof-of-concept experiments with FPGA chips and a fabricated switched-capacitor converter (SCVR). Another major focus of this dissertation involves an in-depth analysis of 3D PDN design with V-S. The first many-layered 3D PDN model (3D-Voltspot), with V-S and differential SCVR, has been developed in a collaborative effort to perform wide-range PDN tradeoff studies, characterizing V-S noise and system power efficiency with varying workloads.