Abstract
The Internet-of-Things (IoT) is a maturing technological revolution that is creating new hardware applications in consumer, commercial, and industrial spaces to collect information and generate insights for a variety of benefits. Exponential early growth of the IoT has seen billions of integrated hardware sensing nodes, or “IoT nodes” deployed into action, but this number falls short of early predictions by over an order of magnitude. A major factor preventing the IoT from reaching its originally-projected size is the finite operating lifetime of nodes that are powered by batteries. A node goes offline or “dies” when its battery runs out of charge, and the cost to replace batteries becomes prohibitive as the IoT continues to grow in size. In response to this challenge, there is a growing focus on extending the lifetime of IoT nodes by reducing their power consumption and harvesting ambient energy to reduce or eliminate their dependence on batteries. In the latter case, battery-free or “self-powered” operation can be sustained as long as a node harvests more power than it consumes, and is an attractive solution for enhancing long-term IoT growth. However, without further reducing the power consumption of IoT nodes, the conditions for self-powered operation are currently only met in a fraction of the total applications when high amounts of power can be harvested.
This research makes several contributions to enable self-powered operation in a larger number of IoT applications by investigating integrated circuit design techniques for maximum power reduction. The scope of investigation is on the microcontroller system which forms the data-processing backbone of an IoT node and consists of a digital processor along with its supporting hardware such as memory, clocking circuits, and input-output peripherals. For digital and memory circuits that are limited by subthreshold leakage currents, a Dynamic Leakage Suppression (DLS) logic style is investigated for low-power operation. A theoretical background and design methodology for DLS logic is derived, and a fabricated test chip is used for experimental verification. Next, a performance-scalable DLS variant is implemented in RISC-V processor and demonstrated in a microcontroller test chip. The application of DLS is extended to memories, and a bitcell implementation of DLS logic demonstrated in a 16kb Static Random-Access Memory (SRAM) chip. For low-power input-output interfacing, a level converter design based on DLS logic is fabricated and shown to enable low-power signal conversion across a wide voltage range. For clocking circuits, several transistor and architectural-level techniques are explored to reduce power consumption across a wide frequency range. A Hz-range oscillator is designed that leverages tunneling currents through the gate oxide as a low power biasing source. A Frequency-Locked Loop (FLL) design is used for kHz-MHz range operation, and theoretical models are derived for power, energy, and temperature stability. New analog and digital FLL architectures are designed and fabricated that use frequency multiplication and duty-cycling for power reduction.
