Pre-RTL On-Chip Power Delivery Modeling and Analysis

The power delivery network (PDN) is the electrical system that provides supply voltage to the transistors within a silicon chip. Due to the PDN’s intrinsic resistance, capacitance, and inductance, the supply voltage can become noisy (drop or fluctuate) and cause timing errors, threatening program correctness. While CMOS technology scaling has resulted in exponentially greater transistor densities, threshold and supply voltages no longer decrease fast enough to prevent exponential growth in on-chip power density. Although the technology of three-dimensional integrated circuit provides an alternative path toward the continued historical trend of device integration growth, it further increases the aggregated power density by stacking active silicon layers on top of each other. As a result, power-delivery-related reliability issues are increasing, creating higher demands for the already scarce physical resources like controlled collapse chip connection (C4) pads and silicon area for the integrated on-chip decoupling capacitors. Unfortunately, there often exists a contention between power delivery needs and processor computation needs. Under these rising challenges, it becomes increasingly important to consider PDN design and optimization at early design stages, both to ensure an optimal design point selection in the complicated tradeoff space, and to prevent costly redesign due to power delivery issues.
In this dissertation, we build and validate a pre-RTL PDN model, called VoltSpot, to (1) identify the power-delivery difficulties for contemporary and near-future microprocessors; (2) understand the impact of PDN’s physical resource allocations on voltage noise and explore the resulting tradeoff space considering the processor’s performance and lifetime under electromigration stress; (3) design and evaluate both static and dynamic solutions to mitigate power delivery constraints; (4) assess the benefits and costs of novel power delivery schemes for 3D-IC.