Abstract
The increasing demand for energy-efficient electronic devices, particularly in the Internet of Things (IoT), has driven significant advancements in low-power circuit design. IoT sensing devices are critical for collecting real-time data to monitor environmental, industrial, and personal conditions, enabling automation, efficiency, and data-driven decision-making [4] [5]. To ensure longevity and effectiveness, these devices must operate with minimal power consumption and ensure their compactness. This shifts the focus from relying on large batteries to optimizing the energy efficiency of the circuits themselves to meet these design considerations [3] [8]. One of the primary challenges in achieving this efficiency is managing leakage currents, which become increasingly problematic as we scale to smaller nodes due to reduced gate oxide thickness and short-channel effects. Leakage manifests in various forms, including subthreshold leakage, gate tunneling leakage, and junction leakage, all of which compound as design complexity increases [1] [2] [10].
This work proposes an approach to mitigating leakage at the transistor level by leveraging I/O devices to design a low-leakage standard cell library. By employing thick oxide devices in constructing these foundational digital building blocks, leakage reduction, specifically gate leakage, is achieved at the source, enabling cascading benefits as designs scale to higher levels of abstraction [11]. This strategy results in compounding power savings across entire systems, making it ideal for applications where energy efficiency is paramount, such as IoT, wearable electronics, and high-performance embedded computing [6]. Furthermore, additional leakage management techniques, such as power gating, can complement the proposed approach, which selectively disconnects idle circuits from the power supply to eliminate static leakage [12]. The synergy between thick oxide I/O devices and power gating ensures efficient power management across various operational scenarios [16].
This work bridges the gap between device-level optimization and system-wide power efficiency by addressing leakage at the transistor level. The proposed low-leakage standard cell library is an enabler for extending the battery life of IoT devices and enhancing the sustainability of energy-constrained systems [9].
