Power Management Techniques in Sub-Microwatt Scalable Systems-on-Chip for Self-Powered Internet-of-Things Applications

With the rapid development of the Internet-of-Things (IoT) technology, the number of connected sensor nodes is projected to increase up to 30 billion by 2027. This surge in IoT devices promises diverse applications, spanning healthcare monitoring, wearable electronics, smart homes, and sustainable urban development. However, the pervasive deployment of IoT devices is hindered by the challenge of battery replacement. To truly usher in the IoT era, electronic devices require to be 1) ultra-low power (ULP) and energy efficient to match the shrinking size of energy sources; 2) self-powered and autonomous to reduce the cost of maintenance. For applications where performance is regulated in the face of scarce ambient energy, a dedicated tradeoff between power and performance becomes imperative. Therefore, the design of system-on-chip (SoC) and the power management unit (PMU) is becoming critical, especially when the physical size of the IoT nodes diminishes down to mm-scale level.

This dissertation tackles these challenges through circuit, system, and architecture-level design techniques to achieve sub-uW and scalable SoCs, with improved energy efficiency and performance for self-powered operations. The thesis delves into design techniques from both the PMU and system perspectives, which covers the entire energy delivery chain from input to output and all types of switching PMU. Various techniques, including energy-performance scaling, energy computation, cooperative power management, dedicated communication protocols, and distributed architecture, have been explored. By implementing these techniques in an ULP and miniaturized manner, the energy efficiency, viability, and scalability of a self-powered system can be significantly enhanced. The dissertation encompasses five research works, detailed below.

1) A fully self-contained, 802 pW, 93% peak efficiency inductor-based PMU chip with a proposed hybrid synchronous and asynchronous control loop which achieves us-level fast load transient responses and fast dynamic voltage and frequency scaling (DVFS) for the first time at sub-nW power scale.

2) An 194 nW energy-performance-aware SoC with a 5.2 nW triple mode PMU that enables energy-performance self-adapting and scaling, fast DVFS, and high accuracy minimum energy point tracking with >100x power overhead reduction compared with state-of-the-arts (SOTA). Furthermore, two ULP IoT hardware that are built upon the proposed scalable SoC are prototyped and validated.

The rest projects focus on mm-scale size self-powered system:

3) A fully-autonomous 33 nW SoC with distributed cooperative energy harvesting and power management for mm-scale fiber system where SoCs can be distributed along a fiber yarn, capable of simultaneously harvesting energy, cooperatively scaling performance, sharing power, and booting-up with other SoCs in-fiber. With the proposed architecture and switched-capacitor based EHPMU, this chip can survive in a 7x darker environment.

4) A fully autonomous triple-input hybrid-inductor-capacitor multi-output EHPMU that can harvest energy from two inputs (thermal and photovoltaic energy), regulate three custom output rails, adaptively switch among multi-conversion methods, cold startup from all the inputs/outputs, and enable energy recycling and sharing among multiple rails. This EHPMU achieves a lowest 5.8 nA quiescent current, a widest dynamic range of 8.8x10^4, and a >90% reduction in inductor size using a 3x3x1.3 mm 200 mΩ inductor.

5) A dedicated wireline communication protocol, named as “bypass Serial Peripheral Interface (SPI)”, achieving flexible and ULP in-textile communication and chip identification management with a fixed 4 wires regardless of the number of nodes connected to the textile. A customized chip is designed and fabricated to validate this protocol, achieving the highest efficiency and lowest quiescent power with enhanced expandability compared to SOTA.