Abstract
The rapid growth of portable mobile devices such as smartphones, smartwatches, wearable health monitors, etc. suggests that the total number of Internet of Things (IoT) devices may reach 50 billion by the year 2020. Depending on the application such as mobile health monitoring, artificial organs, vision for visually impaired people, etc., portability and form factors of such IoT devices restrict the use of energy sources to smaller batteries. Additionally, these mobile devices could run on harvested energy from ambient light, body heat, etc. energy sources, which makes them highly energy-constrained. As energy depends quadratically on the supply voltage, dynamic voltage and frequency scaling (DVFS) reduce energy consumption drastically and boost performance from time to time when needed. Using DVFS, battery-operated IoT devices could duty-cycle the on-chip resources and save energy, to result in longer battery-life. To satisfy this requirement both logic and memory in the IoT system on chips (SoC) must be flexible to operate at such reduced supply voltages. With technology scaling, the logic's minimum operating voltage (VMIN) scales easily with supply voltage. However, process variation increases with technology scaling, which poses a threat to lowering the VMIN of widely used static random access memory (SRAM). Thus, there is a bottleneck for DVFS in area-efficient low-cost SoCs where SRAM and the processor core share the same power rail. Moreover, SRAMs could consume 20%-60% power in IoT SoCs, which requires VMIN lowering techniques to drastically reduce the SRAM power consumption, such as using alternative bitcell topologies, peripheral assist circuits, etc. Furthermore, these solutions could use methodologies, such as design-for-the-worst-case to add voltage and timing guard-bands to cope with the process variation. On the other hand, these techniques have energy and area overheads and require careful design based on low-power specification. Moreover, with technology scaling the high-density (HD) 6T SRAM suffers from write and read issues in FinFET processes at the nominal supply voltages for the worst-case corner. Thus, HD 6T FinFET SRAMs require additional voltage guard-bands to the VMIN for safer operations. SRAM VMIN is also hard to track because it varies with process, frequency, temperature, etc. parameter fluctuations. Canary SRAMs have been shown to monitor SRAM data retention voltage (DRV) VMIN, which could help track the SRAM dynamic VMIN for energy savings. Therefore, exploring these design knobs related to the SRAM VMIN lowering could reveal important tradeoffs from energy efficiency, delay, and area standpoints for IoT applications.
One of the goals of this dissertation is to investigate the circuit and architecture methods to design energy efficient low VMIN SRAMs by tweaking these design knobs. These knobs such as bitcell typologies, peripheral assist techniques, and architectures could push the boundary of the SRAM design space. In the first chapter, we discuss the state of the art trends and challenges in energy efficient and low-VMIN SRAMs for ultra-low-power (ULP) IoT applications and describe the major contributions of this thesis and its organization. The second chapter investigates the scope for improvements in the existing bitcell topologies, array architecture knobs, and a peripheral architecture using a read-modify-write scheme to improve the SRAM read energy efficiency by 5.7X for the ULP sub-threshold applications. In the third chapter, we study the single and dual combinations of peripheral write and read assist techniques for lowering SRAM VMIN in 14nm 6T HD FinFET SRAMs. The fourth chapter introduces the concept of SRAM dynamic write VMIN tracking using canary SRAM and investigates the relationship between the input design knobs of canary and core SRAM and their output metrics. It further documents the tradeoffs of a reverse assist (RA) for canaries to track SRAM VMIN, which could result in a 50% energy savings in 28nm technology. In chapter five, we further show the first proof of concept of RA-based canaries in silicon and examine how sensitive it is to the voltage, frequency, and temperature variation for a VMIN tracking application. In the sixth chapter, we investigate the classification of reverse assists using pulse-shaping techniques for wordline and bitline type RAs in pursuit of VMIN tracking. We further compare their sensitivity properties across canary design knobs and investigate the energy and area tradeoffs of RA circuits. The seventh chapter proposes an architecture, which leverages combined peripheral assists with an in-situ canary-based self-tuning scheme to give 0.38V-1.2V wide-range SRAM. The SRAM architecture achieves a maximum of 1444X active power and 12X leakage savings compared to the nominal supply voltage. Chapter eight proposes a mathematical framework and a set of algorithms to analyze and design RA-based canaries. It further automates and reduces the burden of the analysis and design of RAs across canary design knobs from months to days. Finally, we conclude this thesis in chapter nine, by documenting the summary of contributions, open questions, and discussing the impact of these works.
