CAD and Circuit Techniques for Ultra Low Power, Variation-Aware SRAM Design
Author:
Beshay, Peter, Electrical Engineering - School of Engineering and Applied Science, University of Virginia
Beshay, Peter, Electrical Engineering - School of Engineering and Applied Science, University of Virginia
Advisor:
Calhoun, Benton, Electrical Engineering, University of Virginia
Calhoun, Benton, Electrical Engineering, University of Virginia
Abstract:
Process variations are a main challenge in the design of SRAM in advanced technology nodes, and can limit the minimum supply voltage and the minimum energy consumption. In this work, we focused on circuits that combat these variations effect to enable ultra-low power operation. In addition, we proposed a CAD scheme to co-optimize the architecture and circuit structure of the SRAM to further achieve optimal low power operation.
Degree:
MS (Master of Science)
MS (Master of Science)
Keywords:
Circuit/Architecture co-design, SRAM, Low power design, ViPro, Adaptive stability, Simulated annealing, Convex optimization, offset compensation, wordline control, SRAM Design Optimization, Dynamic margin sensor, Calibration, auto-zeroing, SCOT, wordline quantization, sense amplifier
Circuit/Architecture co-design, SRAM, Low power design, ViPro, Adaptive stability, Simulated annealing, Convex optimization, offset compensation, wordline control, SRAM Design Optimization, Dynamic margin sensor, Calibration, auto-zeroing, SCOT, wordline quantization, sense amplifier
Language:
English
English
Rights:
All rights reserved (no additional license for public reuse)
All rights reserved (no additional license for public reuse)
Issued Date:
2014/11/24
2014/11/24
