Synthesis Based Design Techniques for Robust, Energy Efficient Subthreshold Circuits

Energy efficiency is increasingly becoming the main concern for many emerging system-on-chip (SoC) applications such as those for wireless sensor networks (WSNs) or portable electronics, which require ultra low power and high energy efficiency. Though voltage scaling down to near-(NVt) and sub-threshold(sub-Vt) supply voltages has provided drastic quadratic savings in dynamic energy, design of circuits at ultra low voltages (ULVs) still poses important challenges.
In this work, we focus on robust design for subthreshold circuits while maintaining high energy efficiency. The design techniques span from architecture level, to timing/logic, to transistor level circuit design of standard cells. We first investigate the energy efficiency vs. module platform flexibility design space to answer the question how much energy efficiency is available in each type platform (general purpose processor, FPGA, or ASIC) in being the main driving force behind digital processing on the architecture level. On the timing/logic level, we propose a method for estimating the amount of variation for any given logic path. We explore a two-phase latch based timing method that lowers energy overhead of timing closure. Lastly, we delve into circuit design for ultra low power SoCs, and question the need for a new robust circuit topology to design standard cells for ULV.
Our overall hypothesis is that the success of these projects will enable robust, energy efficient designs in the ULV region, and increase the recognition of ULV designs as viable solutions to industry related problems.