Multi-VT Cell Implementation and Physical Design Optimization for Power-Efficient SoC Design 131 views

Emerging application domains such as edge-AI, wearable health monitors, and textile-integrated electronics demand System-on-Chip (SoC) designs that are not only compact and responsive but also highly power-efficient. To address this challenge, this work proposes a structured design-space exploration methodology that begins at the RTL level and systematically investigates the impact of critical physical implementation choices such as threshold voltage (VT) cell selection and synthesis constraints on overall power, performance, and area (PPA) metrics. Rather than treating these knobs in isolation, this work explores how combinations of choices like hybrid VT deployment, clock timing constraints, and uncertainty margins can be used to achieve optimized trade-offs for application-specific needs. Through a series of controlled experiments, this work shows to quantify the impact of each design knob on power and timing behavior and propose generalizable insights that can guide technology-aware decision-making steps. The results show that selective use of high-VT cells in non-critical paths and regular-VT cells in timing-sensitive regions, when paired with thoughtful constraint tuning, can yield significant reductions in power while preserving system performance and area efficiency.

MS (Master of Science)

English

All rights reserved by the author (no additional license for public reuse)

2025-11-26