Ultra-Low Power, Sub-sqmm Chiplets: Digital Circuits, Architectures, and Design Methods for Resource-Constrained Platforms 196 views

Emerging resource-constrained computing platforms (such as batteryless/energy harvesting systems, E-textiles,Wireless Sensor Nodes (WSN)) are increasingly important in realizing breakthrough systems for industrial, medical, agricultural, environmental, and other applications - traditionally realized on relatively resource-rich platforms. Implementing the necessary functions effectively within extremely limited budget of power/area without sacrificing performance is very challenging - due to the inherent power-performance-area (PPA) trade-offs, and requires exploring all the design trade-offs across the system stack (from firmware, microarchitecture to circuits) to determine the limits of what is realizable. This thesis contributes on these fronts through: i) digital circuit design methods that improves the PPA improvement of highly energy constrained, ultra-low power (ULP) energy harvesting System-on-Chips (SoC) beyond state of the art, by introducing and leveraging sub-quadratic relation between delay and fan-in size of Dynamic Leakage Suppression (DLS) stdcells - popularly used in such applications; ii) design methodologies at architectural and application levels that minimize chip area and maximize performance (like audio recording quality and/or energy-efficient communication throughput) of highly area constrained, fiber-integrable, tiny chiplets for long-term, comfortable, wearable, functional E-textiles; and iii) design techniques and methodologies at system and block levels of SoCs that improve the performance metrics of the highly power constrained WSN and IoT application platforms.

PHD (Doctor of Philosophy)

High Fan-in; E-textiles; Audio compression; ADPCM; CIC; WuRx; Wakeup Receiver; 2.4 GHz ISM; 24 GHz K Band; I2C ; SPI; I2C to SPI converter; TAuC-SoC Tiny Audio Compressor SoC; WuTRX Wakeup Transceiver; Thermal Diffusion ; Zero calibration; Linear WSN; multi-hopping; DLS Dynamic Leakage Suppression; SDLS Scalable Dynamic Leakage Suppression; Resource constrained platform; energy harvesting; Ultra-Low Power ULP; M0+ Cortex ARM; RISCV ; Elmore delay; delay scaling with fan-in size; highly area constrained; highly power constrained; distributed hierarchical network; compute communication pipeline; audio computation complexity; STIPA STOI; Temperature sensor; Programmable voltage current reference

English

2026-04-15