Design and Analysis of the On-Chip Power Delivery Network for Energy Efficient Systems 876 views

One of the most important metrics in modern digital integrated circuit design is energy efficiency. Energy efficiency is loosely defined as completing an application’s workload at the lowest possible energy while still maintaining the desired performance. Energy efficiency is an important metric across the entire application space, from high-end applications to low-end applications. For example, high-end applications are limited by heat constraints in both personal and commercial computing. Low-end applications are not limited by the power wall but are instead constrained by application lifetime due to limited battery capacity. In this dissertation, we demonstrate two scaling techniques that modify the local on-chip power delivery network to enable voltage scaling and energy efficient operation. The first technique, a programmable resistive power grid, creates a low overhead programmable power grid resistance by modifying the on-chip power delivery network. To achieve a programmable resistance, we break a monolithic power switch into partitions with independent gate control. The second technique, Panoptic Dynamic Voltage Scaling (PDVS), modifies the power delivery network at the component level by adding multiple PMOS power switches and a discrete set of shared VDDs. This allows each component to operate at the best VDD depending on the application requirement. Next, this dissertation demonstrates architectural and power delivery techniques to enable subthreshold operation in a voltage scalable system. We present a methodology for adapting PDVS architectures (or similar) for subthreshold operation. We propose using an NMOS header power switch with a nominal VDD gate control to enable subthreshold operation. For designs with variable VDDs, a transmission gate power switch provides the most robust power switch configuration. Finally, this dissertation presents an energy efficient research and design infrastructure. This infrastructure leverages a set of scripts for commercial EDA tools and documentation to provide a fast and reliable methodology for power delivery network design space exploration. The scripted infrastructure also enables a fast and reliable methodology for creating large System on Chip (SoC) designs.

PHD (Doctor of Philosophy)

All rights reserved (no additional license for public reuse)

2014-04-09