Dynamic Reconfigurable Deep Neural Network Accelerator

Deep learning is a really hot topic because of its massive computation power and has already been used in many areas, such as automobile, stock price prediction, image processing, etc. Under this circumstance, improving the DNN's performance and power efficiency... is eagerly needed, which blossomed plenty of Deep Neural Network Accelerators. All of these accelerators are trying to optimize the metrics that people care about. However, different DNNs(Deep Neural Networks) have different input and output dimensions. Even the data size of different layers in the same DNN are mainly diverse, which means that the accelerators mentioned previously need to map the changeable input data dimension to the fixed hardware resource. We proposed a new architecture that is made of a lot of PEs(Processor Elements) under the foundation of Systolic Array and the shape of this PE Array can be dynamically changed during DNN layer execution, which could make the hardware part more possible to meet with the changeable requirement of different input data dimensions.