Abstract
Wireless sensor nodes for Internet-of-Things (IoT) applications collect information in a variety of consumer, commercial, and industrial applications such as wearable electronics, healthcare monitoring, smart homes etc. These aim to dramatically improve our quality of life and productivity. However, the proliferation of such IoT networks has been hindered by the increase in cost of deployment due to limited operational lifetimes of its nodes. This is because it becomes prohibitively expensive to change the batteries of dead nodes in ever growing networks. In addition, since IoT applications differ greatly in the type of sensing and data collection and consequently their circuit implementation and power budgets, there are challenges related to design complexity, manual engineering design, time-to-market constraints, and the requirement for number of functional blocks. Therefore, there is a strong need to develop solutions that allow fast and cost-effective generation of low power circuits that can run on ambient energy, thereby reducing, or eliminating their need for a battery. This research aims to enable self-powered operation in a larger number of IoT applications by investigating and modelling integrated circuit design techniques for maximum power optimization in memory circuits, creating ultra-low power memory circuits, and enabling rapid generation of analog and mixed signal circuits using digitally synthesizable unit-cell-based approach.
In this work, we aim to model the minimum operating voltage (VMIN) and the various design variables in an SRAM for rapid designing and power optimization. In particular, the statistics of design variables in the critical path of the SRAM read and write operation that greatly affect the minimum operating voltage (VMIN) are studied and modelled. A statistical model is developed that provides quick (~15 sec) estimation of failure probability and the corresponding VMIN for a given SRAM design with low error (<6%). The model is also used to create a dataset (with ~160K unique SRAM design points) in 20 hours, to observe the effect of various SRAM design variables, quantize their importance and determine inter-variable correlation.
Next, we design a new memory bit-cell that uses cross-coupled Dynamic Logic Suppression (DLS) logic inverters to significantly reduce the leakage power of the memory to enable lower power budget for an SoC or IoT node. The new bit-cell allows to retain pW to nW power budget at higher supply voltages without depending on aggressive supply voltage scaling to retain higher performance. The design and performance of the DLS inverter pair is analyzed from this context to ensure reliable operation. Two SRAM implementations (2KB and 6KB) are developed for use with the DLS bit-cell, and are fabricated in a 65nm test chips. The 2KB DLS SRAM consumes 52pW (at 0.3V) to 132pW (at 0.9V) and the 6KB version consumes 618pW (at 0.3V) and 10.1nW (at 0.9V), thereby enabling nW operation for IoT nodes. Another SRAM is implemented using Scalable Dynamic Logic Suppression (SDLS) logic inverters to enable high performance during access mode, while simultaneously retaining low power in stand-by mode. Simulation results show performance ranging from 3.5KHz (at 0.3V) to up to 10MHz (0.7V) with a leakage power of 1.8nW to 23nW respectively.
Finally, to address the ever-growing need for automation in analog circuit design and integration to meet modern- day IoT SoC requirements, we propose methodologies to synthesize correct-by-construction RTL descriptions for both analog and mixed signal circuits using a unit-cell-based approach. We apply these methods to SRAM and Low Dropout Voltage Regulator (LDO) as proof of concept. Several prototypes are implemented in 65nm bulk planar CMOS and 12nm FinFET technologies. A large reduction is observed in the manual effort from several weeks/months to just a few hours with minimal loss of performance compared to manual design efforts.
