Abstract
Modern computing touches nearly every aspect of human lives, with applications from desktops, laptops, smartphones, automobiles, and the Internet of Things (IoT). The primary driver of pervasive computing is the complicated Mixed-signal systems-on-chips (SoCs). The proliferation of computing with a wide range of applications, from ultra-low power devices such as body sensor networks (BSNs) and IoT to high-performance applications, made the mixed-signal SoCs design space application-centric. The system requirements of these SoCs vary across applications, and one-SoC-fits-all is no longer sufficient. This requirement necessitates the custom design of SoCs per application, translating to the SoC hardware design’s complexity and massive design effort. One of the reasons for such an effort is the custom design of the SRAM and the AMS components to meet various needs across the SoC design space, which is typically the bottleneck for SoC design cycles as the design process of these components is generally manual. The current state-of-the-art hardware design approaches increase the system costs and the time to market, creating a hardware bottleneck for the broad adoption of ubiquitous computing applications.
This research makes several contributions to address the hardware bottleneck through cell-based design methodologies and frameworks that collectively enable the autonomous synthesis of SoC components across a broad range of application space, from ultra-low power (ULP) devices to high-performance applications, thus reducing SoC design time and enabling faster time to market. First, an SRAM bitcell generator is implemented to auto-generate the ULP bitcell from high-level SRAM macro specifications. Tunable assist circuits are developed to dynamically adapt the assist percentage as a function of system VDD for reliable SRAM operation in a DVFS SoC. The output of this work is an embedded sub-threshold memory capable of operating down to 0.45V. Furthermore, we evaluated the effect of the read and write-assist methods on SRAM minimum operating voltage (VMIN) and Yield for a FinFET high-density (HD) bitcell and proposed the assist combinations with high VMIN improvement.
Next, we developed a technology-agnostic and open-source SRAM memory framework called MemGen. MemGen is a framework that auto-generates SRAM memories across a broad range of voltages, frequencies, and capacities using conventional digital tool flows in less than five hours instead of months of custom-design time and with less than 15% area penalty compared to the commercial memory compilers. The modular tool flow allows a novice designer to use it in a “push-button” mode, automatically generating the SRAM from the high-level user specifications without the user diving into the device, architecture, and circuit-level details. It also allows expert designers to augment the tool with new architectures and circuits to expand the design space supported by the generator.
Finally, we created an auxiliary cell generator (AuxcellGen) that automates the generation of optimized auxcells for the memory and AMS component generators and fills the missing piece of a fully autonomous SoC synthesis tool. It reduces the porting time between technologies to less than two days instead of weeks to months of manual porting time. More importantly, it helps expand the design space supported by the MemGen and the other AMS component generators by auto-generating the optimized auxcells for user-defined cell specifications.
