Systems on Chip (SoC) for Body Sensor Nodes: A System Level Approach 1264 views

The last 20 years have seen the development of several technologies that individually play an important role to enable Wireless Sensor Nodes to become a reality. First, the energy consumption has been reduced to the order of decades of $\mu W$ thanks to digital and analog ultra-low power circuits that are able to operate reliably in the subthreshold regime. Second, the ability to harvest energy from the environment eliminates the dependency on bulky batteries and elongates the life of sensor nodes. These sensors must support sensing modalities and processing capabilities for a broad range of applications that can go from the most commonly showcased ECG (Electrocardiogram) to more demanding applications as wheezing detection for asthma management. All these components considerably increment the design complexity associated with these highly integrated SoCs. Developing a node for each application with the current RTL methodologies is not possible due to the prohibitive Non Recurring Costs (NRE) associated with the design and verification of such a complex systems. On the other hand, it has been proven that the optimum operation point for an ultra low power system highly depends on the application and the activity factor associated with it, thus a platform optimum for one application might be sub-optimal or not suitable for others. This scenario raises awareness to a question that has not been explored yet in the sensor nodes literature, "How do we efficiently integrate these complex Systems On Chip (SoCs) taking into account the application particular requirements". This thesis explores these system level questions associated with SoC design and proposes two complementing approaches to address them. First, we design a re-use and verification aware methodology for wireless sensor nodes. This methodology uses interface based design and block abstraction. The combination of these two techniques, enable RTL configurability at the system level to meet particular application requirements, and allow hardware evolution/modification reducing the design NRE costs. We applied this methodology during the integration of a 6.45 uW Self-Powered IoT SoC with Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios. This SoC has the highest level of integration to its publication date. Second, inspired by the necessity of a system level approach, that covers architecture exploration and application validation in wireless sensor nodes, we setup an Application Oriented framework. This framework facilitates the communication between the algorithm developer, the hardware designer and the hardware verifier in order to explore the hardware trade-offs associated to a particular application. We called this framework AVEBoS and is intended for early exploration or late validation. Early exploration is needed so the architecture is defined taking into account the requirements of one or a set of applications. Late validation is required to evaluate the performance of the node for a particular application under a specified condition. Using this framework and the re-use ideas explored for the SoC integration, we design, verified and evaluated the performance of a Short Time Fourier Transform accelerator for wheezing detection and a FFT-IFFT based 6 uW Pulse Oximetry Digital Signal Processing Data Path. Following these system level strategies we expect to optimize the engineering effort invested in a single SoC, to start paving the path towards an architecture that gives birth to a family of SoCs able to adapt to different application requirements and operation conditions with a design cost that is spread across different solutions by the use of truly re-usable IP.

MS (Master of Science)

systemverilog; Subthreshold; System level integration; VLSI; verilog; SoC; abstraction; Ultralow power; BSN; verification; IoT; Internet of things

English

All rights reserved (no additional license for public reuse)

2015-11-19