Towards Cost-Effective Thermal Management Method for Processing in 3D Memory

As Moore's law states, the number of transistors in an integrated circuit doubles every two years. The increase in transistor density and operating frequency produces heat problems in semiconductor devices, limiting further advancements. To resolve thermal issues, the performance criteria in modern computing have transitioned from higher frequency and denser transistors to more advanced integration processes, algorithms, and architecture. However, due to data‐intensive computing, the performance has been degraded from the bandwidth limitation between processor and memory. Processing‐in‐memory and 3D chiplet are preeminent solutions for the degraded performance due to the "memory wall." Processing‐in‐memory prevents performance degradation by migrating a portion of the computation load to the memory, while 3D chiplet integration does this by shortening data movement and increasing bandwidth. The high bandwidth memory is a 3D integrated circuit with memory dies stacked on top of a logic die. The 3D-stacked memory is the core technology in processing-in-memory architecture and is a region where thermal issues usually occur in the 3D chiplets. The computation in the 3D-stacked memory induces a higher power density in the 3D stacks. The higher power density increases the volumetric heat flux, while the heat sink removes the heat only from the top surface. This volumetric thermal hazard also occurs in other 3D chiplets in the same manner. To manage thermal issues in 3D semiconductor devices, a thermal management solution with a cost-efficient volumetric cooling system is essential.
In this dissertation, we propose a new thermal management method with microfluidic cooling to enable processing in-3D-memory. This dissertation presents the thermal management solution in two aspects: device design and thermal simulation. In the device research aspect, we develop a cost‐effective microchamber cooling structure for 3D‐stacked memory devices. While the conventional microchannel method has a high fabrication cost due to the additional fluidic structures, the proposed method reduces the fabrication cost by exploiting the gap between the upper and lower stacks and the 3D printing package. We demonstrate the validity of the microfluidic chamber cooling method with an experimental setup. The prototype shows the feasibility of the proposed method. In the second part of this study, we simulate the thermal behavior of the 3D chiplet with the microfluidic cooling system. First, we model the thermal characteristics of the 3D stacked memory from a 4‐layer stack to a high‐rise stack. For further investigation, we use HotSpot for fast and accurate thermal simulation. We run thermal simulations using HotSpot in different cooling configurations for a processing-in-3D-memory system, where memory layers sit on top of a logic layer. The HotSpot simulation results are validated with a Multi‐Physics simulation, COMSOL. When a detailed fluidic behavior is observed, the cooling capacity of the microfluidic cooling system is degraded by the thermal boundary. We minimized the impact of the thermal boundary layer by creating a more detailed thermal model of the fluidic chamber with micropillars inserted.
We investigate the thermal characteristics of modern chiplet systems. The temperature of the 3D stacked high-performance processors has significantly increased from that of the 2.5D integration. We lower the temperature below the operating temperature limit by implementing novel thermal management methods such as alternating flow directions and applying multi-layer cooling. We also investigate a heterogeneous processor-memory chiplet system in 2.5D and 3D integration. While the heatsink cooling system cannot maintain the temperature of the 3D chiplet below the operating temperature limit, the microfluidic cooling system reduces the temperature with a cost-affordable hybrid cooling method. We conclude that our proposed thermal management method provides a cost-effective and 3D chiplet-compatible solution that guides chip designers and architects in understanding the thermal behavior of modern computing devices.