An Analysis of a Symmetric Circuit Topology for Ultra-Low Power Voltage Scaling in Deep Nanoscale CMOS

As integrated circuits (ICs) continue to scale, power consumption has become an important concern, making sub-threshold (sub-VT) operation an attractive route for ultra-low power (ULP) applications, especially those that harvest energy from the environment. However, a major roadblock lies in increased sensitivity to process variations both at near- and sub-VT. Additionally, temperature variations can be detrimental to circuit functionality for energy harvesting applications operating in outdoor environments. This vulnerability to variations at the device level is exacerbated by imbalances between pull-up (PUN) and pull-down (PDN) networks at the circuit level. This thesis presents a symmetric circuit topology in conjunction with a biasing scheme that maintains symmetrically robust operation of ULP energy harvesting systems in a variety of climates, including extreme temperatures. Through noise-analysis and Monte Carlo (MC) simulations performed in a commercial 28nm Fully Depleted Silicon On Insulator (FDSOI) technology, the robustness to variations and extreme temperature ranges of the proposed symmetric 2-to-1 multiplexer design (mirror mux) with bias is demonstrated and compared to conventional 2-input NAND and NOR-based circuits. The linearity between temperature and bias makes this scheme easily applicable for programmable sensors in a variety of applications requiring environmental adaptability.