Techniques for Design of Compact and Efficient Digital Doherty CMOS Power Amplifiers and Transmitters

The Sub-7 GHz spectrum (450 MHz to 7 GHz) is widely used for a variety of wireless communication networks. Over the years, the use of this spectrum has evolved heavily to support increased connectivity and higher data-rates. Various emerging applications such as smart home connectivity, augmented reality, virtual reality, smart farming, inventory tracking, and industrial monitoring, have led to the creation of newer networks, such as 5G cellular, Wi-Fi 6E, and Wi-Fi HaLow. Despite the vastly different operations of these networks, all of them share a common need for cost-effective devices with long battery life. Transmitters are one of the most important components of a wireless device since they directly affect both of these attributes through their size and power dissipation. Therefore, this dissertation focuses on frequency and output power scalable design techniques to realize compact and efficient wireless transmitters.

In recent years, digitally implemented transmitter architectures have garnered a significant amount of interest as they are amenable to scale with process nodes, and they have the potential to achieve improved battery life while being cost-effective. However, in practice, the battery life improvement is severely limited, as these architectures suffer from poor efficiency in output power back-off. Further, the two well-known digital transmitter implementations, polar and quadrature, have their own limitations. The polar implementation suffers from wide bandwidth expansion that limits the overall data-rate of the transmitter, while the quadrature implementation exhibits degraded efficiency due to the enormous in-phase/quadrature basis vector overlap, which further limits the improvement to battery life.

This dissertation proposes and implements two techniques, a nested Doherty architecture and a transformer-within-transformer Doherty architecture, to improve efficiency in deep power back-off, while still achieving a compact form-factor to enable cost-effective transmitters. In addition, a multi-phase current-mode implementation of a digital power amplifier is also proposed and implemented to achieve higher data-rates, while also improving the overall efficiency, to improve the battery life of the transmitter even further. These techniques are demonstrated using two different integrated circuit chips implemented in a general-purpose 65 nm CMOS process:

1) A four-way asymmetric digital polar power amplifier shows an implementation of a four-way nested Doherty architecture to achieve efficiency enhancement up to 9 dB in output power back-off, while maintaining a compact form-factor, for IoT-type applications around 5 GHz.
2) An asymmetric current-mode eight-phase digital Doherty transmitter using a single footprint transformer-based matching network shows an implementation of a transformer-within-transformer Doherty architecture to achieve efficiency enhancement up to 9.5 dB output power back-off, while also realizing a compact form-factor. Additionally, it highlights the implementation of an eight-phase architecture to improve the efficiency profile compared to its quadrature counterpart, for high data-rate applications around 6.5 GHz, such as WiFi 6E.