Abstract
The information technology sector has experienced explosive growth in data-intensive applications such as bioinformatics, big data analytics, and deep neural networks (DNNs). These computing tasks have a tremendous economic impact and societal benefits, but their execution on conventional Von Neumann architectures is inefficient due to excessive data movement, a problem that rapidly growing input data sizes have exacerbated. To tackle this bottleneck, the computer architecture research community has put forward many data-centric solutions that place logic inside memory or the disk drive, commonly referred to as Near-data-processing (NDP), to reduce the latency and energy cost of data access significantly. Additionally, NDP architectures usually offer much larger parallelism, higher data bandwidth, and lower peak power consumption than CPU and GPU. This allows them to achieve orders of magnitude speedup and energy saving when executing data-intensive kernels.
This dissertation outlines four new contributions to NDP, including (1) a digital bit-serial DRAM-based processing scheme that targets a wide range of computing tasks, including bioinformatics, data analytics, pattern matching, and general-purpose arithmetic, (2) a 3D-stacked memory technology with an integrated compute layer that accelerates de novo genome assembly, (3) a processing-with-storage-technology (PWST) HW/SW codesigned framework that targets k -mer counting, a key bottleneck of many bioinformatics tasks, and (4) a case study of how privacy and data integrity can be breached in a recent NDP-based DNN accelerator leveraging the non-volatile memory technologies (NVM), highlighting the importance of fostering future NDP accelerator design with a security focus.
