Nanomagnetic Memory and Logic: Energy-delay-reliability Trade-Off

The ability to rotate the magnetization of a single domain nanomagnet using spin polarized current or uniaxial strain leads to exciting possibilities for low-power embedded memory and logic applications. Realizing those applications for real life usage requires addressing a complex and interlinked set of problems: material properties of the ferromagnet-oxide heterostructure, spin transport, micromagnetics and thermal stochasticity of the free layer. A particular challenge the STT-RAM industry faces is maintaining a high thermal stability while trying to switch within a given voltage pulse with an acceptably low error rate and energy cost. While operating at lower barrier increases the static error in STT-RAMs, it decreases the dynamic write error rate associated with the spins freezing around stagnation points along the potential energy landscape of the nanomagnets. We introduce a comprehensive and predictive STT-RAM modeling platform that operates at different levels of complexities, ranging from a quasi-analytical model for the energy-delay-reliability trade-offs to a fully atomistic, chemistry based multi-orbital model for predictive material design and optimization. Using this platform, we identify suitable alloys for perpendicular, in-plane and partially perpendicular magnets, identify the advantages and trade-offs with double barrier junctions, and underscore the dual role of thermal fluctuations, both in hindering rotation and also in releasing spins from their stagnation points. A similar set of challenges confronts ‘straintronics based multiferroic logic, where once again thermal perturbations play a decisive role on the dynamic writing error rate. In presence of stagnation points, applied stress, demagnetization field and dipole-dipole interactions, the error rate and switching delay can be controlled by material design and by engineering the stress profile on the nanomagnets.