Abstract
The internet-of-things (IoT) is playing a role in revolutionizing human life by providing a network of devices with smart sensors, actuators, and network connectivity. Reliable systems with diverse functionality are in demand for a wide variety of IoT applications, for instance, healthcare, smart building, and computer vision. As billions of IoT devices are emerging in every corner of the world, there is a need for low-cost systems capable of sensing, processing, storing, and transmitting data. Ultra-low power (ULP) is a necessary feature for such systems because it is too costly and impractical to frequently replace or recharge the vast number of batteries to power these devices. In the quickly evolving battery-less systems, the power from energy harvesters also cannot reliably sustain high-power-consumption solutions. To address the dilemma between the growing need for greater functionality and lower power consumption, we propose to develop a full series of cutting-edge ULP integrated circuit (IC) components, such as subthreshold embedded static random access memory (SRAM), wake-up receivers (WURX), clock references, and deep neural network (DNN) hardware accelerators, to enable low-cost and ULP IoT systems. These four IC components are studied because they are critical circuit blocks for achieving the ULP operations of IoT system-on-chip (SoCs), and they can employ different low-power techniques to effectively reduce the system power consumption.
Circuit modeling plays a vital role in guaranteeing reliable operations in the subthreshold region, speeding up the design period, predicting the circuit and system performance, and guiding the direction for design improvements. The challenges of designing reliable and ULP IC components are dramatically different from the traditional performance-driven IC designs because the performance of CMOS devices is more sensitive to the process variation in the near or subthreshold region.
SRAM could consume up to 50% of the power consumed by an IoT system, so it is desirable to operate in the subthreshold region to suppress the active and the standby power, where it also faces read and write reliability issues. The SRAM yield analysis model utilizes the normal distribution feature and the importance sampling of SRAM metrics to estimate the bit error rate (BER) of different failure types by speeding up the simulation time by 10,000x compared to the conventional Monte Carlo simulation. An SRAM bitcell auto-generation flow and an SRAM macro design exploration tool are proposed to smartly make design decisions for a 2 KB SRAM testchip in the 65 nm technology while satisfying user requirements and guaranteeing reliability in the subthreshold region.
WURXs could relieve the burden of milli-watt level power dissipation of the radio system by waking up the primary receiver from the idle mode rather than being active all the time. The challenges of designing a nano-watt level WURX are improving the sensitivity for remote wake-up signals and rejecting the false alarms. We propose a correlator wake-up code model to guide the WURX's baseband circuit design and improve the sensitivity by choosing appropriate comparator threshold voltages and correlator wake-up codes. Assisted by the robust baseband circuit, our WURX taped-out in the 130 nm technology achieves a -76 dBm sensitivity and less than one false wake-up (FWU) per hour at 10 nW of power consumption.
Commercial radio systems such as the Bluetooth low-energy (BLE) system require an off-chip crystal as the super-stable clock reference, which increases the cost and bulkiness of IoT devices. On-chip clock references design is extremely challenging because the requirement of frequency stability needs to be less than 150 ppm across the process, voltage, and temperature (PVT) corners. We propose two circuit models to improve the temperature and supply voltage stability of RC relaxation oscillators (ROSC). An on-chip ROSC with both analog and digital frequency compensation is taped-out in the 65 nm technology, and it achieves a temperature coefficient (TC) of 2.5 ppm/°C and an absolute variation of 100 ppm over the body-compatible range of 0 to 40°C. The supply voltage stability is also improved by 30% with a simple outside capacitor. Power consumption of the ROSC is reduced from 69 μW to 100 nW by supporting the power gating technique.
DNN hardware accelerators as the artificial intelligence (AI) inference computing engine are appealing for supporting computer vision applications in IoT systems. In-memory computing (IMC) is a new DNN computing architecture that can relieve the data movement issue of von Neumann architectures, thus potentially achieving energy-efficient computation. However, the process variation of the on-chip memory bitcells and the noise in the mixed-signal computation introduce precision degradation of DNN inference. We propose an IMC accuracy model to guide the direction for choosing appropriate memory micro-architectures and to predict the impact of IMC accuracy loss on the DNN inference precision. A 30 fJ per multiplication and accumulation (MAC) SRAM-based IMC architecture with binary weights and 2-bit activations is predicted by the proposed accuracy loss model to achieve 97.7% precision in the hand-written digit recognition.
