Highly Reconfigurable and High Sensitivity Wake-up Receivers with Aggressive Duty-Cycling Techniques

Author: ORCID icon orcid.org/0000-0003-3466-5994
Dissanayake, Anjana, Electrical Engineering - School of Engineering and Applied Science, University of Virginia
Calhoun, Benton, EN-Elec/Computer Engr Dept, University of Virginia
Bowers, Steven, EN-Elec/Computer Engr Dept, University of Virginia

Ultra-low power sensor nodes are vital for large scale Internet-of-Things (IoT) sensing applications. A typical IoT sensor node may consist of a micro-controller, wireless transceivers, sensor interfaces, and a power-management unit. The continuous operation with high instantaneous power node components can quickly overwhelm the available energy sources, which limits the operational lifetime. Low activity factor IoT networks can adopt periodic duty-cycling to reduce the average node power consumption at the cost of latency. However, periodic duty-cycling can be inefficient if the node information is accessed in an infrequent event-driven manner. A wireless wake-up receiver with negligible power consumption was proposed as an optimal solution to improve the node lifetime by providing event-driven duty cycling capability instead of a local wake-up timer based approach.

The prior wake-up receiver work has largely investigated the envelope-detector first (ED-1st) topology. The sub-GHz operation can enable wide area networks due to the low path loss, even though the optimum operation requires a large antenna and reliance on off-chip components. The ED-1st topology at sub-GHz range demonstrated sub micro-watt dc-power beneficial for longer node lifetime, but the maximum sensitivity was limited near -81dBm. However, the industrial IoT applications spanning several kilo-meters scale networks, such as agriculture, farming, and forest monitoring, require sensitivities near -100dBm, which cannot be achieved by the ED-1st topology. As the frequency is scaled to multi-GHz range to benefit from a smaller antenna and high integration, the sensitivity of the ED-1st quickly diminishes due to the lack of available high-quality factor components. Moreover, the reconfigurability with respect to the sensitivity, dc-power, and latency, is highly impactful due to the diverse application space of IoT and numerous unforeseen post-deployment variations. However, the ED-1st does not readily lend to the reconfigurability aspect, and the inherent sensitivity limitation and frequency scaling difficulties call for alternate solutions.

Addressing above issues, this dissertation presents highly reconfigurable and high sensitivity wakeup receiver design techniques. The research in this dissertation explores two architectures, the tuned-RF (T-RF) and the uncertain-IF (U-IF) as alternate solutions beyond the ED-1st topology. Both the T-RF and U-IF require high power active components and requires duty-cycling to maintain low power. This dissertation explores the limitations of two asynchronous duty-cycling techniques, the bit-level duty cycling and packet-level duty cycling, to reduce the dc-power to sub-microwatt levels while maintaining desirably low latencies.

The bit-level duty cycling technique has been demonstrated with sub-GHz T-RF topology in three separate proof of concept CMOS prototypes and trade-offs between the sensitivity, power, and latency are explored. This dissertation demonstrates that heterogenous integration of the T-RF with a noise limiting narrowband micro-electromechanical system (MEMS) based filter can boost the wake-up receiver sensitivity beyond -100dBm while maintaining sub-microwatt level power at hundreds of milli-seconds latencies. When the noise limiting filter is omitted, the T-RF suffers from a high dc-offset at the rectifier output due to the noise self-mixing effect. This work demonstrates that an envelope modulated signaling scheme capable of IF channelization can alleviate the dc-offset issues. An IF channelization method without the need of a complex multi-tone transmission is used to demonstrate the multi-channel operation in a nano-watt scale T-RF wakeup receiver.

The packet-level duty cycling technique has been investigated with a highly integrated U-IF wake-up receiver operating at the 2.4GHz ISM band. This work demonstrates that an integrated PLL based event-driven calibrated RF oscillator in a U-IF front-end can enable a sensitivity of -93.5dBm without external calibration. The work also demonstrates that in a low-activity factor network, the received signal strength-based within-packet duty cycling can be used achieve dc-power as low as 2μW at 100ms latency with a 540μW instantaneous power of the U-IF receiver. These contributions can enable 2.4GHz ISM band wake-up receiver solutions suitable for low-throughput event-driven IoT applications.

Overall, the prior wake-up receiver research has produced an abundance of literature but found limited commercial applications. This can be attributed to the fact that each IoT application requiring a dedicated wake-up receiver due to the unique user constraints. This dissertation attempts to address the above issue by providing insightful guidelines on selecting the best possible wake-up receiver topology for a given set of application constraints. This is done by 1) relating various user specifications to the WuRX performance metrics, 2) identifying the various trade-offs associated with several popular WuRX topologies and duty-cycling schemes, and 3) selecting the topology closest to the requirements with the aid of a design space analysis of reported wake-up receiver performance. The method proposed in this dissertation can serve as a tool for IoT system planning with respect to selecting the optimum wake-up receiver topology.

PHD (Doctor of Philosophy)
Wake-up Receiver, Ultra-Low Power, Duty-Cycled, Tuned-RF, Uncertain-IF

This research was funded in part by Defense Advanced Research Projects Agency (DARPA) Near Zero Power RF and Sensor Operations (N-ZERO) program, National Science Foundation (NSF) ASSIST Center, and Viasat Virginia-Beach Program.

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